1. Field of the Invention
The present invention relates to a semiconductor memory device and, more specifically, it relates to a semiconductor memory device which is capable of preventing access delay due to the fluctuation of the supply voltage.
2. Description of the Prior Art
FIG. 1 is a block diagram showing a conventional static RAM (Random Access Memory) as an example of a semiconductor memory device.
Referring to FIG. 1, the static RAM 21 comprises an I/O bus line 25 connected to the memory cell array 28 and an I/O bus control circuit 23 for controlling the I/O bus line 25. The I/O bus line 25 is connected so as to receive a column address signal Yi at the column decoder 26. A data input buffer 32 and a data output buffer 33 are also connected to the I/O bus line 25. An external chip select signal ext.CS which is the signal for externally controlling the state of the static RAM is applied to the clock generator 24 through a CS buffer 22. The clock generator 24 generates a clock signal .phi. in response to the signal ext.CS. The I/O bus control circuit 23 controls the I/O bus line 25 in response to the clock signal .phi. from the clock generator 24. The description of other circuits shown in FIG. 1 will be omitted.
FIG. 2 is a schematic diagram showing in more detail the I/O bus line 25 and the I/O bus line control circuit 23 shown in FIG. 1. The I/O bus line 25 comprises two I/O lines 251 and 252, and n channel field effect transistors 31 to 3n and 41 to 4n for connecting the bit lines 281 to 28n of the memory array 28 with the I/O lines 251 and 252. Column address signals Yl to Yn are respectively applied to the gate of each of the transistors. The I/O bus line control circuit 23 comprises n channel field effect transistors 1 and 2 constituting the load of the I/O lines 251 and 252, a p channel field effect transistor 5 for equalizing the I/O lines 251 and 252, and an equalizing signal generator 23 for generating the equalizing signal IOEQ in response to the clock signal .phi.. Both transistors 1 and 2 have their respective gates and drains connected together to the power supply V.sub.cc. The transistor 5 is connected between the two I/O lines 251 and 252 with the equalizing signal IOEQ applied to the gate thereof.
The provision of a load such as the transistors 1 and 2 of FIG. 2 between the I/O line and the power supply is known as the circuit technique required for implementing high speed operation of the semiconductor memory device. For example, similar circuit technique can be seen in the Japanese Patent Publication Gazette No. 5989/1984 and in the Japanese Patent Laying-Open Gazette No. 229788/1984. This technique has been recently applied to the dynamic RAM which is capable of static column mode.
FIGS. 3 and 4 are timing charts for describing the operation of the static RAM shown in FIG. 2. FIG. 3 shows the case in which the supply voltage has no fluctuation while FIG. 4 shows the case in which the supply voltage has fluctuation. V.sub.cc denotes the voltage level of the power supply V.sub.cc and V.sub.ss shows the voltage level of the ground, respectively.
The operation of the static RAM with no fluctuation of the supply voltage will be hereinafter described with reference to FIGS. 2 and 3.
First, the static RAM is in the standby state due to the application of high level external chip select signal ext.CS. In the standby state, the I/O lines 251 and 252 are brought to the voltage of V.sub.cc -V.sub.T by the transistors 1 and 2. V.sub.cc is the value of the power supply V.sub.cc and V.sub.T is the threshold voltage value of the transistors 1 and 2. The transistor 5 turns on in response to a low level equalizing signal IOEQ to bring the two I/O line 251 and 252 at the same voltage. When the signal ext.CS changes to the low level and the signal IOEQ changes to the high level, the signal stored in a certain memory cell (for example, MC1) of the memory array is applied to the I/O lines 251 and 252 through the bit line 281. The solid line and the dotted line in FIG. 3 show that the two I/O lines 251 and 252 are brought to the different voltages. On this occasion, since the transistors 1 and 2 serving as the I/O line load are connected to the I/O lines 251 and 252, the I/O lines to which a low level signal is applied are not fully brought to the ground V.sub.ss level. Although the voltage difference between the two I/O lines 251 and 252 is small, this is amplified by a highly sensitive current mirror type sense amplifier, so that the high speed operation of the static RAM is possible. In addition, the range of the voltage change of the I/O lines is narrowed down by the I/O line load, so that faster operation of equalization or precharge is possible. Meanwhile, the method of precharging the I/O line to the same level as the supply voltage V.sub.cc may be applied as an alternative; however, it is not preferred since the sensitivity of the current mirror type sense amplifier decreases due to the characteristics. In addition, since the transistors 31 and 41 operate in response to the column address signal Y1 having a high level signal of the voltage level, that is V.sub.cc, for example, the high speed operation of the transistors 31 and 41 is prevented if the I/O lines 251 and 252 are brought to the same voltage level as the supply voltage level. Therefore, the method is popularly used in which the I/O lines 251 and 252 are brought to the intermediate potential such as V.sub.cc -V.sub.T in the standby period.
The operation of the static RAM with the fluctuation of supply voltage will be hereinafter described with reference to FIGS. 2 and 4.
In the case shown in FIG. 4, in the standby period, namely, when the signal ext.CS is at a high level, the supply voltage changes from a high level value V.sub.cc (H) to a low level value V.sub.cc (L). Even after the supply voltage changed to the value of V.sub.cc (L), the I/O lines 251 and 252 are continuously brought to the high level voltage, that is, V.sub.cc (H)-V.sub.T.
When the signal ext.CS changes to the low level, namely, the active operation starts, and the memory cell signal is first read to the I/O lines 251 and 252, the sensitivity of the sense amplifier decreases to cause an access delay. More specifically, the supply voltage applied to the sense amplifier is provided with the reduced V.sub.cc (L) level voltage while the voltage of the I/O lines 251 and 252 will be the level changed from the V.sub.cc (H) level by the signal from the memory cell. Therefore, the sense amplifier operates being off the optimal range of operation, so that the sensitivity is reduced and it takes much time to read the data on the I/O lines 251 and 252. In addition, as is specifically shown by the dotted line in FIG. 4, it takes much time to stabilize the voltage level of the I/O line to which a low level signal is applied from the memory cell, and, as shown by the solid line in FIG. 4, the equalization comes to an end before the two I/O lines 251 and 252 attain the same voltage value. The foregoing also causes the access delay.